IC Figure below shows the 8-to-1 multiplexer Integrated circuit of TTL family This Integrated circuit has active LOW ENABLE input and gives. Texas Instruments [ KB ]; Data Sheet (current) [88 KB ]; Fairchild Semiconductors [58 KB ]; Data Sheet (current) [ KB ] 8-Input Multiplexer IC. I3, 1 •, 16, Vcc. I2, 2, 15, I4. I1, 3, 14, I5. I0, 4, 13, I6. Y, 5, 12, I7. Y, 6, 11, S0. E, 7, 10, S1. GND, 8, 9, S2. Pin, Symbol, Description. 1, I3, multiplexer input.
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A common multiplexer is the 8: Various multiplexers are available in discrete chips as well for both series and series. A single inverter is used 774151 invert the selection line value to one of the gates so that only one of them e.
A truth table is provided on the right.
Multiplexer (MUX) – WikiChip
A set of inputs called select lines determine which input should be passed to the output. One can use a multiplexer to select which of those lines should be going to the shared data bus.
Typically larger multiplxers over 8 or 16 inputs are built using smaller multiplxers using a multiplexer tree. There are many way to construct 7151 4: Even in ASIC design, arbitrary sized multiplexers are not always offered.
Pins 5 and 6 are the outputs, the output on pin 6 is the inverted version of the output on pin 5.
IC pinout diagram – Integrated Circuits
The top transmission gate controls if the input from A should pass to the output while the bottom transmission gate does the same for the B input.
Additionally multiplexers have also found their way to various other circuits such as adders. A set of select lines are then used to choose ci of those inputs gets produced as output. While smaller overall, this multiplexer is also nonrestoring. A multiplexer with 2 N input lines requires N select lines. A 71451 is a device that receives multiple inputs from usually different sources.
MULTIPLEXER IC 74151
Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. This page was last modified on 18 Novemberat Such multiplexer can be design from four 8: Note that the iic below is an active-low.
Those types of multiplexers can be hooked up directly to a shared bus ensuring that only one signal is being generated on the bus at any given time.
MUX with an SR latch.
The simplest multiplexer is the 2: It does mean that for multiplexers with odd number of inputs, some selection line combinations are not allowed e. For a multiplexer with Equation upper N inputs, you also need Equation left ceiling log Subscript 2 Baseline left-parenthesis upper N right-parenthesis right ceiling selection lines.
From there the sum of minterms and the logic function for a 2: For example, consider a data bus that is connected to multiple memory storage 7411.
Where Equation m Subscript k is the kth minterm of the variable. The K-Map for that truth table is provided on the left.